Phase-locked loops (PLLs) have been applied to many applications ranging from generating clock signals in microprocessors to synthesizing frequencies. In general, a PLL may include a voltage-controlled oscillator (VCO) that generates an output signal with a frequency that is locked onto a frequency of a reference signal. To lock the frequency of the output signal with the frequency of the input signal, a MI may include a phase detector (PD) configured to compare the phase of the reference signal to the phase of an output signal generated by the oscillator, and to generate a PD output that is proportional to the phase difference between the phase of the input signal and the phase of the output signal.
Through the feedback of the output signal to the PD, the PLL drives the frequency of the output signal to the frequency of the input signal and locks the phase of the output signal with the phase of the input signal. The PLL may also assist in correcting any phase misalignment resulting from internal or external noise sources.
The use of PLLs on interfaces is becoming snore common as speeds increase and precise timing is required. Upon power up, reset, or a frequency change, PLLs may have a “settling time” to lock the phase and/or frequency of the output signal to the phase and/or frequency of the input signal and stabilize the PLL. Depending on the phase and/or frequency mismatch between the output phase and the input signal the settling time may vary.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.